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| LIBRARY: Papers |
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Franz Gisin, Estimation of Potential ESD Failure Rates
in an Uncontrolled Operating Environment |
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Summary |
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Often the assumption is made that ESD events above the highest mandated test voltage, such as those specified in ESD test standard EN 61000-4-2, occur at such infrequent intervals that they can, for all intents and purposes, be ignored. [1] But in many cases, device failure rates increase at a faster rate with increasing voltage than the decrease in the number of ESD events, in which case a significant ESD failure rate can still be experienced during normal operation even though the device complies with the applicable ESD test standards.
A more accurate assessment of ESD failure rate, than merely showing compliance to a given test standard, is to multiply the number of ESD events that occur at a given voltage level by the probability that the ESD event at that voltage can cause device failure. If the probability of device failure increases at a faster rate with increasing voltage than the decrease in ESD event frequency, then the potential threat from ESD event voltages higher than the required maximum compliance test level can be the dominant source of ESD failures during normal device operation. |
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Introduction |
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Most electronic products destined for distribution worldwide must be tested for compliance with ESD standard EN 61000-4-2. Referring to Table 1, this standard defines four air discharge test environments (classes) that are characterized by their lowest relative humidity, whether antistatic material is present or absent, and whether ESD generating synthetic materials are present or absent. |
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| Table 1: EN 61000-4-2 Guidelines for Selecting Maximum Test Level |
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| Class (Test Level) |
Relative Humidity as low as % |
Antistatic Material Present |
Synthetic Material Present |
Maximum Test Voltage KV |
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| 1 |
35 |
x |
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2 |
| 2 |
10 |
x |
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4 |
| 3 |
50 |
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x |
8 |
| 4 |
10 |
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x |
15 |
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Because most small hand-held devices spend much of their operational lives in Class 4 “uncontrolled” environments, they must be tested to a maximum level of 15 KV. But even though they are tested to this maximum level, it does not guarantee that ESD related failures will never occur during normal operation. For example, ANSI Standard C63.16- 1991, defines expressions for computing ESD event frequency in an uncontrolled environment - similar to the Class 4 level defined in Table 1 – as a function of the ESD event voltage. [2][3] Based on these expressions, more than 100 ESD events between 15 KV and 30 KV can occur during the estimated 2 year life of a hand-held device. Unless additional measures are taken to protect the device to levels higher than the 15 KV test level, field failures due to ESD can continue to create costly product returns and replacement problems for the manufacturers and distributors of these devices. [4]
While the frequency of ESD events decreases with increasing voltage, the threat level is not independent of the test voltage. A 15 KV or 30 KV ESD event has a much higher probability of causing a device to malfunction than a 2 KV ESD event. So even though a device designed to pass the mandated 15 KV test level will be immune to the majority of ESD events that the device will be exposed to during its life, it will not be protected against the higher voltage ESD events that have the highest probability of causing the most damage. This is because |
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higher voltage ESD events have a higher chance of breaking through (arcing) any natural barriers provided by the device’s enclosure, |
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the increased energy inherent in these higher voltage ESD events can more easily “zap” ICs and other static sensitive devices, |
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and higher voltage ESD event have a higher probability of arcing to interconnects (for example, traces on a PCB) that are not protected by discrete static-protection devices. |
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Referring to Figure 1, if the device’s ESD failure rate increases at a higher rate than the decrease in the ESD event rate, then the net risk, which is the product of the product of these two rates, increases with increasing ESD event voltage. In this case, compliance to standards such as EN61000-4-2 does not guarantee no device failures during normal operation. |
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Figure 1: Calculating Net Risk from ESD Event and Device Failure Rates |
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Detailed Discussion |
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Referring to Table 1, the maximum test voltage increases in roughly 1 octave increments. [Class 2 is double Class 1, Class 3 is double Class 2, Class 4 is approximately double Class 3.] By extending the upper limit one more octave, to 30 KV, one can obtain a more accurate assessment of how the untested ESD events above 15 KV impact the probability of potential ESD failure rates in an uncontrolled environment.
Estimating the potential number of ESD failures as a function of ESD event voltage level can be made by multiplying the ESD event rate, EV, by the probability, PA, that the ESD event is capable of arcing across (through) an aperture, seam, slot or exposed connector in the device’s enclosure, and the probability, PE, that the energy in the ESD event is high enough to cause device circuits to malfunction. |
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ESD Event Frequency, EV |
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The expected number of air discharge ESD events occurring in an uncontrolled environment can be calculated using the equations given in ANSI C63.14, “Guidelines for Electrostatic Discharge Test Methodologies and Criteria for Electronic Equipment”. [3] From ANSI C63.14, the expected number of air discharge ESD events occurring during a given hour in an uncontrolled environment at a voltage greater than, V, is given by |
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From this, one can compute the expected number of events within a voltage range, Vnominal - ΔV to Vnominal, by |
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For example, the expected voltage within the range of 5 KV and 6 KV can be approximated by |
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Once the number of ESD events per hour are found using Eqn 3, the total number of ESD events expected during the lifetime of the device can be easily found. Figure 2 plots the number of ESD events that can be expected to occur in an uncontrolled environment over a 2 year period. Actual values are also tabulated in Appendix A, Table A1, Column 2. |
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Figure 2: Estimated number of ESD events expected to occur in an uncontrolled environment |
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Probability of Failure due to Arcing, PA |
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It is easier for higher ESD voltages to arc into the device through connector openings, enclosure seams and slots, and openings required for visual indicators such as LEDs. Devices that have a large number of connectors for connection to external devices and are constructed utilizing a large number of fixed or moveable enclosure components are especially susceptible to discharging directly to internal circuits through enclosure openings. Once the discharge reaches the internal circuits, options to limit where the discharge currents are allowed to flow can be difficult to control, increasing the risk that sensitive ICs can be damaged by the discharge currents.
For devices with only a single aperture, the probability of arcing though an aperture, PA, can be expressed by a simple step function. Below the breakdown voltage, no arcing occurs. Above the breakdown voltage, arcing will occur. Most devices, however, do not have a single aperture, and these apertures will invariably break down at different levels.
Consider, for example, the hypothetical example of a device that has five apertures, each one breaking down at a successively higher voltage level. As the test voltage is increased beyond the lowest level aperture, arcing to internal circuits through that aperture can potentially occur. As the test voltage is increased beyond the second lowest level aperture, arcing to internal circuits can now occur at two apertures (the lowest and the second lowest). This cumulative process can continue until the test voltage exceed the highest level aperture, in which case all five apertures are no longer capable of isolating ESD events from arcing to internal circuits.
In the limiting case, the probability of arcing directly to circuits inside a device, PA, can be approximated by a probability function that is proportional to the voltage, V, of the ESD event. In other words, a 20 KV ESD event has twice the probability of arcing across an enclosure barrier as a 10KV ESD event. Mathematically, this can be expressed as |
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For the uncontrolled environment example given in this white paper, one can set Vmax = 30 KV. |
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[It should be noted that there can be considerable deviation from this linear model for individual device designs. However, if the sample space is enlarged to include all devices within a particular product line (say, for example, all cell phone models), then this approximation becomes accurate enough to warrant serious consideration.] Table A1, Column 3 lists the probability, PA, of an arc-related failure as a function of ESD event voltage. |
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Probability of Failure Due to ESD Event Energy, PE |
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The energy contained in an ESD event increases with the square of the voltage. For example, the energy stored in the 150 pF capacitor of an ESD gun complying with [1] is given by |
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Where C is the capacitance and V is the voltage. In this context, the energy of a 20 KV ESD event is four times higher than the energy in a 10 KV event. [Those familiar with ESD testing, quickly notice that the sparks created by higher voltage ESD events are not only physically longer, but also much fatter, brighter and louder.]
The probability of a failure due to the increased energy in the ESD event can thus be expressed as |
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For the uncontrolled environment example given in this white paper, Emax = E30KV. Table A1, Column 4 lists PE as a function of ESD event voltage. |
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Normalized Risk |
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Multiplying the ESD event frequency, probability of arcing into the device, and probability of circuit malfunction due to excessively high event discharge energy and normalizing by the sum over all voltages, one arrive at a percent risk potential as a function of ESD voltage. Referring to Table A2, Columns 5 and 6, one can see that even though a predominant number of ESD events occur at lower voltages, the potential for causing device malfunction increases with increasing event voltage. Based on the analysis presented herein, a significantly large portion of the ESD threat is due to ESD event voltages that are not measured during an actual EN 61000-4-2 test. |
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Number of Circuits or Traces Protected |
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Up to this point, the assumption has been made that protection to a given level results in all circuits (ICs, etc.) - that are susceptible to ESD events - are protected to that particular level. This may not be the case if the primary protection approach is based on just protecting those circuits that malfunctioned during the ESD test using, for example, discrete protection devices.
Many devices also exhibit time windows, where the device is more susceptible to ESD events during certain operations than others. For example, memory devices can exhibit different ESD sensitivity levels during setup, read and write cycles. Whether the limited number of ESD events induced during an ESD test captures the most sensitive mode is always a lively topic of discussion in EMC circles.
For example, independent product tear-down studies of cell phones have shown that discrete ESD protection circuits typically only protect 2 – 3 % of the circuits populating a device’s main PCB. While these discrete ESD protection devices can be used to ensure protection at levels less than 15 KV, they cannot be guaranteed to provide the additional protection required for ESD events greater than 15 KV. In this case, the impact of protecting a larger number of circuits or traces than what is afforded by the discrete ESD protection devices is necessary.
One way to accomplish this is to employ a PCB- level protection approach such as XStatic™ that not only provides virtually 100% coverage, but also has the capacity to absorb the much higher energy levels associated with 20 KV to 30 KV ESD events. |
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References |
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EN61000-4-2, Electromagnetic Compatibility (EMC), Part 4, Testing and Measurement Techniques, Section 4.2, Electrostatic Discharge Immunity Test – Basic EMC Publication. |
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ANSI C63.16-1991, “Guidelines for Electrostatic Discharge Test Methodologies and Criteria for Electronic Equipment”. |
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“Performing Statistical ESD Tests Using ANSI C63.14-1991 Guide for ESD Test Methodologies”, T.J. Ritenour and Franz Gisin, IEEE International Symposium on Electromagnetic Compatibility, 1992. |
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“Flash Memory Field Failure Mechanisms”, Pekka Muroc, Nokia Corporation, IEEE 44th Annual International Reliability Physics Symposium, San Jose, California, 2006. |
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Appendix A: Tabulation of Detailed ESD Analysis Values |
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| Table A1: Summary of ESD Analysis |
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| 1 |
2 |
3 |
4 |
5 |
6 |
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| ESD Event Voltage |
EV # ESD Events Over 2 Years |
PA Probability of Arcing |
PE Probability of High Energy Failure |
Normalized Risk Potential |
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| 2 |
5419 |
6.7% |
0.1% |
0.7% |
0.7% |
| 3 |
1251 |
10.0% |
0.5% |
1.8% |
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| 4 |
512 |
13.3% |
1.1% |
3.0% |
2.3% |
| 5 |
269 |
16.7% |
1.9% |
4.5% |
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| 6 |
163 |
20.0% |
3.0% |
6.2% |
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| 7 |
108 |
23.3% |
4.3% |
8.0% |
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| 8 |
76 |
26.7% |
5.8% |
10.1% |
7.1% |
| 9 |
57 |
30.0% |
7.8% |
12.3% |
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| 10 |
44 |
33.3% |
9.6% |
14.8% |
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| 11 |
35 |
36.7% |
11.9% |
17.4% |
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| 12 |
28 |
40.0% |
14.4% |
20.1% |
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| 13 |
23 |
43.3% |
17.1% |
23.1% |
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| 14 |
19 |
46.7% |
20.1% |
26.2% |
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| 15 |
16 |
50.0% |
23.3% |
29.5% |
19.4% |
| 16 |
14 |
53.3% |
26.8% |
33.0% |
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| 17 |
12 |
56.7% |
30.4% |
36.7% |
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| 18 |
11 |
60.0% |
34.4% |
40.5% |
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| 19 |
10 |
63.3% |
38.5% |
44.5% |
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| 20 |
8.5 |
66.7% |
42.9% |
48.7% |
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| 21 |
7.6 |
70.0% |
47.6% |
53.0% |
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| 22 |
6.8 |
73.3% |
52.4% |
57.6% |
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| 23 |
6.2 |
76.7% |
57.6% |
62.3% |
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| 24 |
5.6 |
80.0% |
62.9% |
67.1% |
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| 25 |
5.1 |
83.3% |
68.5% |
72.2% |
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| 26 |
4.7 |
86.7% |
74.3% |
77.4% |
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| 27 |
4.3 |
90.0% |
80.4% |
82.8% |
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| 28 |
4.0 |
93.3% |
86.7% |
88.4% |
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| 29 |
3.7 |
96.7% |
93.2% |
94.1% |
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| 30 |
3.4 |
100.0% |
100.0% |
100.0% |
70.5% |
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